Enhanced security semiconductor device, semiconductor circuit arrangement and method or production thereof

ABSTRACT

A semiconductor circuit arrangement providing enhanced security has a first circuitry portion ( 12 ) on a semiconductor wafer ( 10 ), a second circuitry portion ( 16 ) on the wafer separate from the first circuitry portion, the second circuitry portion being coupled ( 26 ) to the first circuitry portion and containing access circuitry for allowing access to thereto, and the second circuitry portion being disposed on the wafer such that it can be destructively removed therefrom to leave the first portion of semiconductor circuitry inaccessible through the second portion of semiconductor circuitry. Isolation circuitry ( 30 ) is provided for electrically isolating the first circuitry portion following destructive removal of the second circuitry portion.

FIELD OF THE INVENTION

This invention relates generally to semiconductor electronic devicesrequiring enhanced security.

BACKGROUND OF THE INVENTION

Such electronic devices are commonly used to hold data (such as, forexample, financial or personal data) which must be kept secure fromunauthorised access or “hacking”.

It has been proposed to incorporate electronic circuitry for specificsecurity features into the active die area of a semiconductor electronicdevice. However, such a proposal suffers from the disadvantage that theincorporated security circuitry would be visible (under microscopicinspection) to a hacker and would therefore be easier for the hacker toreverse engineer. Also, such incorporated security circuitry could limitthe testability of the device during production, and so could compromiseproduct quality or require significant effort to design and implement anew test philosophy.

It has also been known to separate physical features, such as bond/probepads or test circuitry used for testing during production, from thetested device before the device is shipped from the production facility.Typically the device test mode offers general access to device data andfeatures, and so removing access to the test mode increases the securityof device data. However, these known separation methods merelydisconnect the features, such as bond/probe pads or test circuitry, fromthe device and leave visible and active the remaining conductors andcircuitry. These known separation methods could, therefore, conceivablyallow a hacker who could obtain the separated bond/probe pads or testcircuitry to reconnect or reverse engineer the necessary circuitry togain access to the device's test mode.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a semiconductorcircuit arrangement, a semiconductor device and a method of productionthereof, in which the above disadvantages are overcome or at leastalleviated.

The above object has been achieved by a semiconductor arrangement havinga first circuitry portion, consisting of one or more semiconductor dies,disposed on a semiconductor wafer and a second circuitry portion on thewafer separate from the first circuitry portion. The second circuitryportion is coupled to the first circuitry portion and contains accesscircuitry for allowing access to the first circuitry portion andcontains bond pads for allowing exclusive access to the accesscircuitry. The second circuitry portion is disposed on the wafer suchthat it can be destructively removed therefrom to leave the firstportion of semiconductor circuitry inaccessibe through the secondportion of semiconductor circuitry. Isolation circuitry is provided forelectrical isolation of the first circuitry portion following thedestructive removal of the second circuitry portion.

In accordance with a first aspect of the invention there is provided asemiconductor circuit arrangement as claimed in claim 1.

In accordance with a second aspect of the invention there is provided asemiconductor device as claimed in claim 5.

In accordance with a third aspect of the invention there is provided amethod of producing semiconductor circuitry as claimed in claim 8.

BRIEF DESCRIPTION OF THE DRAWINGS

One electronic device and its method of production will now bedescribed, by way of example only, with reference to the accompanyingdrawings, in which:

FIG. 1 shows a part of a semiconductor wafer containing an array ofelectronic devices and their associated test circuitry, prior toseparation of the individual devices;

FIG. 2 shows an individual electronic device after testing andseparation from the wafer of FIG. 1, and ready for shipping; and

FIG. 3 is a schematic circuit diagram of isolation circuitry which isemployed in the device of FIG. 2 to electrically isolate conductorspreviously used to connect test circuitry during production and testing.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

Referring firstly to FIG. 1, a semiconductor wafer 10 contains an arrayof electronic device dies 12 (four of which devices are shown in thepart of the wafer illustrated in FIG. 1). The electronic device dies 12are identical and each contain memory circuitry 14 for holding datawhich is to be held secure in use of the device in the field. In thispreferred embodiment, the devices are microcontrollers and the memorycircuitry 14 is provided in the form of read-only memory (ROM), but itwill be understood that this invention is more generally applicable toany electronic device in which data is to be held securely.

The wafer is processed using conventional semiconductor fabricationtechniques to form the dies 12 thereon. During this fabrication of thedies 12, test circuitry and bond/probe pads, depicted generally at 16and which will be more fully described hereafter, are formed on thewafer between the dies 12. For reasons which will be explained below,the test circuitry and bond/probe pads 16 are formed within areasbounded by the pairs of dashed lines 18, 20 and 22, 24. The testcircuitry and bond/probe pads 16 are connected to their respectivedevice dies 12 by conductors 26.

When fabrication of the wafer 10 is complete, testing of each individualdevice die 12 is performed by inserting probes to contact the bond/probepads 16, and applying signals to the probed bond/probe pads in order toactivate the device in its test mode and thereby test (in known manner)features of the device, including its memory 14. Such testing isperformed in known manner, and need not be described in further detail,except that (as will be explained hereafter) the conductors 26 requireenabling voltages to be applied to the test circuitry and bond/probepads 16 in order for the conductors not to be isolated.

When testing of each individual device 12 has been satisfactorilycompleted, the wafer is subjected to a first sawing operation: saw cutsare made along and between each of the pairs of dashed lines 18, 20 and22, 24. In this first sawing operation, a saw blade having a width equalto the space between each of the pairs of dashed lines 18, 20 and 22, 24is used to cut at a shallow depth sufficient to cut into the surface ofthe wafer, but not so deep as to cut completely through the wafer. Thissawing operation thus destructively removes all the test circuitry andbond/probe pads 16 between the dashed lines 18, 20 and 22, 24.

It will be appreciated that since the test circuitry and bond/probe padshave been removed from their respective device dies at this point nofurther testing of the device is ordinarily possible. It will be furtherappreciated that since the test circuitry and bond/probe pads aredestroyed in their removal, their visual inspection or reverseengineering is made practically impossible, further enhancing securityof the devices against access by a hacker. It will be still furtherappreciated that the broken, remaining conductors 26 connected to thedevices 12 cannot now be used to probe electrical activity or featuresof the devices since these conductors are now rendered and remainisolated in the absence of the enabling signals from the test circuitry16 which was present but which has now been destroyed.

Finally, the wafer 10 is subjected to a second sawing operation: sawcuts are made along and between each of the pairs of dashed lines 18, 20and 22, 24, along channels left by the first sawing operation. In thissecond sawing operation, a saw blade having a narrower width than in thefirst sawing operation is used to cut completely through the wafer. Thissecond sawing operation thus completely separates the wafer intoindividual device dies, such as shown in FIG. 2, which provide enhancingsecurity against unauthorised access.

Referring now to FIG. 3, as mentioned above, isolation circuitry 30 isprovided in the device die 12. The circuitry 30 comprises a transmissiongate arrangement made up of two field effect transistors (FETs) 32 and34. The FET 32 is a p-channel device, and the FET 34 is an n-channeldevice. The FETs 32 and 34 have their source electrodes connectedtogether and also have their drain electrodes connected together. TheFETs 32 and 34 are connected with their source and drain electrodes inseries in a conductor 26 between the test circuitry 16 and the remainderof the device die 12. The gate electrode of the FET 32 is connected to aconductor from the test circuitry 16; the gate electrode of the FET 34is coupled, via an inverter 36, to the same conductor from the testcircuitry 16.

It will be understood that the circuitry 30 functions as a transmissiongate which, when enabled by at its gate electrodes by an enable signalfrom the test circuitry, allows another signal to pass on the conductor26 between its source and drain electrodes. In the absence of the enablesignal from the test circuitry, the transmission gate circuitry preventsany signal from passing between its source and drain electrodes, and soisolates the associated conductor 26 from the test circuitry.

It will be appreciated that when the test circuitry is destructivelyremoved from the wafer as described above the parts of the conductors 26remaining on the device die 12 are thus electrically isolated from theremainder of the device die. It will therefore be appreciated that, asalready explained above, security of the device against unauthorisedaccess is enhanced since the remaining conductors 26 connected to eachseparated device 12 cannot now be used to probe electrical activity orfeatures of the device.

As shown in the accompanying drawings, by the dashed lines 26, securityof the devices 12 is further enhanced by “burying” (e.g., by implant, orby forming subsequent covering layers) the conductors 26 beneath one ormore layers of insulating material such as silicon nitride so as torender more difficult probing of the contacts or their visual inspectionin the separated devices 12.

It will be appreciated that as alternatives to the above-describedpreferred embodiments, laser obliteration, diamond scribe or additionalwafer processing steps such as selective chemical etching could be usedin place of sawing to destructively remove the test circuitry.

It will further be appreciated that although in the above describedembodiment features in the form of test circuitry and bond/probe padsare destructively removed to enhance the security of the finisheddevice, the security of the finished device could be alternatively oradditionally enhanced by the destructive removal of other features suchas expanded test mode circuitry or circuitry for unscrambling (otherwisescrambled) access to the devices' bus, central processing unit ormemory.

What is claimed is:
 1. A method for providing enhanced security to asemiconductor circuit arrangement comprising: a) providing asemiconductor wafer having a first portion with semiconductor dies and asecond portion separate from the first portion having access circuitryfor allowing access to the first portion of semiconductor circuitry anda plurality of bond pads terminating the access circuitry and allowingaccess to the access circuitry; b) providing conductors electricallycoupling said second portion of said semiconductor wafer to said firstportion of said semiconductor wafer; c) destroying the access circuitryand bond pads of the second semiconductor portion; and d) separating thewafer into individual dies after destroying the access circuitry andbond pads.
 2. The method of claim 1 wherein said step of destroying isinsufficient to cut completely through the wafer, thus maintaining awafer structure.
 3. The method of claim 1 wherein separating the waferinto individual device dies occurs by sawing completely through thewafer.
 4. The method of claim 1 wherein destroying the access circuitryand bond pads is accomplished by sawing partially through said secondportion of said semiconductor wafer.
 5. The method of claim 1 whereindestroying the access circuitry and bond pads is accomplished by laserobliteration.
 6. The method of claim 1 wherein destroying the accesscircuitry and bond pads is accomplished by selective chemical etching.7. The method of claim 1 wherein destroying the access circuitry andbond pads is accomplished by a diamond scribe.
 8. A method of producingsemiconductor circuitry with enhanced security, comprising: a) forming afirst portion of semiconductor circuitry including of one or moresemiconductor dies disposed on a semiconductor wafer; b) forming asecond portion of semiconductor circuitry disposed on the semiconductorwafer separate from the first portion of semiconductor circuitry, thesecond portion of semiconductor circuitry being coupled to the firstportion of semiconductor circuitry by a plurality of conductors, andcontaining test circuitry for allowing access to and testing of thefirst portion of semiconductor circuitry and a plurality of bond padsterminating the test circuitry for allowing exclusive access to the testcircuitry; and c) destructively removing the second portion ofsemiconductor circuitry from the wafer, including the bond pads, toleave the first portion of semiconductor circuitry inaccessible throughthe second portion of semiconductor circuitry wherein said step ofremoving occurs pre-dicing of said wafer.
 9. The method of producingsemiconductor circuitry according to claim 8, wherein the step ofdestructively removing the second portion of semiconductor circuitryfrom the wafer comprises performing a first sawing operation on thesurface of the wafer at a depth sufficient to destructively removing thesecond portion of semiconductor circuitry and insufficient to cutthrough the wafer.
 10. The method of producing semiconductor circuitryaccording to claim 9, further comprising performing a second sawingoperation on the wafer at a depth sufficient to cut through the wafer.11. The method of producing semiconductor circuitry according to claim8, the semiconductor circuitry further comprising isolating circuitryfor electrically isolating the first portion of semiconductor circuitryfollowing removal of the second portion of semiconductor circuitry. 12.The method of producing semiconductor circuitry according to claim 11,wherein the isolating circuitry comprises transmission gate means. 13.The method of producing semiconductor circuitry according to claim 8,further comprising dicing the wafer into individual dies after said stepof destructive removal.
 14. The method of producing semiconductorcircuitry according to claim 8 further comprising burying said pluralityof conductors under at least one layer of insulating material to anextent that the conductors are isolated from probing.